Here, the effect of fin shape on the leakage currents like gate induced drain leakage and subthreshold leakage is evaluated. We derive an analytical expression to estimate the probability density function pdf of the leakage current for stacked devices found in cmos gates. Chandrakasan3 1university of virginia, 2texas instruments, 3massachussetts institute of technology. Characterization of flipflop designs at subthreshold voltages. Effect of fin shape on gidl and subthreshold leakage currents.
Therefore, subthreshold circuit design is very promising for future. A 180mv subthreshold fft processor using a minimum energy. Statistical analysis of subthreshold leakage current for. Direct tunneling gate leakage, which is due to the tunneling of electron or hole from the bulk silicon through the gate oxide potential barrier into the gate. A highdensity subthreshold sram with dataindependent.
Transistors that are supposed to be off actually leak. Body effect is represented by the term v sb, where is the linearized body effect coef. A new subthreshold leakage model is proposed in order to improve the static power estimation in general cmos complex gates. Subthreshold mosfet behavior for analog applications. Electrical characteristics of cylindrical gateallaround. Subthreshold circuit design and optimization proprietary or. Pdf the driving force for the semiconductor industry growth has been the elegant scaling nature of cmos technology.
Subthreshold leakage modeling and reduction techniques author. In recent years, subthreshold operation has gained a lot of attention due to ultra lowpower consumption in applications requiring low to medium performance. Circuit techniques for leakage reduction mixedsignal. The objective is to find the pdf of the subthreshold leakage current for a circuit block or. Since changing tox can also alter the subthreshold leakage current, we have characterized the technology files such that at a given vth, the same subthreshold leakage current, isub, is maintained across the entire range of tox. As part of the modeling approach, we also develop an analytical methodology to estimate the equivalent resistance of mosfet devices in subthreshold regime. Hence, the leakage currents are verified using their expressions for both rectangular and triangular finfets. Variabilityaware design of subthreshold devices uwspace. By applying a high or low voltage on the gate contact, the current flow between source and drain can be switched on or off, respectively. James kao, siva narendra, anantha chandrakasan created date. Drain current equation of mosfet in subthreshold operation.
Device and circuit design challenges in the digital. Subthreshold leakage current reduction techniques for static. Publishers pdf, also known as version of record includes final page, issue and. Circuit techniques for subthreshold leakage reduction in a deep submicron process by benton highsmith calhoun submitted to the department of electrical engineering and computer science on may 24, 2002, in partial fulfillment of the requirements for the degree of master of science in electrical engineering abstract. Subthreshold conduction or subthreshold leakage or subthreshold drain current is the current between the source and drain of a mosfet when the transistor is in subthreshold region, or weakinversion region, that is, for gatetosource voltages below the threshold voltage. A novel synthesis approach for active leakage power.
Subthreshold leakage modeling and reduction techniques. Circuit techniques for leakage reduction 3 v g, v d, v s, and v b are the gate voltage, drain voltage, source voltage, and body voltage of the transistor, respectively. A 55nm ultra low leakage deeply depleted channel technology. A novel synthesis approach for active leakage power reduction using dynamic supply gating swarup bhunia, nilanjan banerjee, qikai chen, hamid mahmoodi, and kaushik roy school of electrical and computer engineering, purdue university, west lafayette. Express briefs, ieee transactions on 565 june 2009 with 158 reads. It is important to estimate both average and maximum power in cmos circuits at different levels of design. However, the subthreshold leakage current, which is known to have an exponential characteristic, has a direct. This exponential relationship is expected to give an exponential reduction in power con.
Pdf fullchip subthreshold leakage power prediction model for. Report cs200305 yan zhang, dharmesh parikh, karthik sankaranarayanan, kevin skadron, mircea stan. Circuit techniques for subthreshold leakage reduction in a. Pdf leakage current reduction using subthreshold source. The subthreshold current is exponentially related to the gate voltage. The fin shape can be changed by varying the top width of the fin. Subthreshold leakage current reduction techniques for.
The framework consists of a complete flow that supports device, gate, and chiplevel leakage analysis, as well as a methodology to characterize leakage related process variations in a systematic manner. As a result, there is an increase in the subthreshold swing and offstate leakage current, which is especially harmful for low power applications. By using the technique, a transistor is optimized for subthreshold operation in terms of the desired total leakage current and intrinsic delay bounds. But gate overdrive vgsvt is also a linear function of vt need to understand vt in more detail to find ways to reduce leakage 1 qv v vgs t. All books are in clear copy here, and all files are secure so dont worry about it. In 6, the authors proposed a subthreshold sram with reduced leakage using highv t devices for the array and standardv t devices for the peripheral circuits to ensure timely signal generation. Robust subthreshold circuit designing using subthreshold. Pdf the large subthreshold leakage current of static cmos logic circuits designed in modern nanometerscale technologies is one of the main barriers. Subthreshold leakage, which is the leakage current from drain to source i sub in figure.
The exponential increase of subthreshold leakage drain current with decreasing vt for a given vgs is shown in equation. However, when combined with dualthreshold and variablethreshold cmos techniques, substantial subthreshold leakage current reduction was also achieved. In this paper we present a method for reducing both subthreshold and gate tunneling leakage current of an sram by using different threshold voltages and oxide. Subthreshold and gate leakage current analysis and reduction in vlsi circuits by vinay chinta a thesis submitted in partial fulfillment of the requirements for the degree of master of science in computer engineering approved by.
This is accomplished by adjusting the vth0 parameters in the hspice model file. Leakage current mechanisms and leakage reduction techniques in deepsubmicrometer cmos circuits kaushik roy, fellow, ieee, saibal mukhopadhyay, student member, ieee, and hamid mahmoodimeimand, student member, ieee contributed paper high leakage current in deepsubmicrometer regimes is becoming a significant contributor to power dissipation of. Read online subthreshold operation and gmid design cppsim book pdf free download link book now. However, the offstate leakage can be utilized as the operating current to achieve ultralowpower applications, such as portable wireless devices, medical devices 23.
Subthreshold mosfet behavior for analog applications current leakages are ever present in electronic systems, and many forms of leakage are considered by engineers to be unusable. The incentive of operating the circuit in subthreshold mode is to be able to exploit the subthreshold leakage current as the operating drive current. Consequently, fast and accurate leakage power estimation models, which are strongly dependent on precise modeling of the stacking effect on subthreshold leakage and gate. Based on our preliminary work, in this paper we propose a framework for fullchip leakage analysis for 65 nm technology and beyond. Dhireesha kudithipudi department of computer engineering kate gleason college of engineering. Subthreshold leakage subthreshold leakage is the most important contributor to static power in cmos note that it is primarily a function of vt higher vt, exponentially less current. Leakage power, including subthreshold leakage power and gate leakage power, is becoming more signi. It has also been shown that by optimizing the device structure, power consumption of digital subthreshold logic can be further minimized while improving its performance. M, using the finite element, numerical method by solving poissons equation in cylindrical coordinate system. Analysis of subthreshold finfet circuits for ultralow power. While using highv t devices reduces leakage these devices suffer from increased variations. Subthreshold and gate leakage current analysis and reduction.
A temperatureaware model of subthreshold and gate leakage for architects univ. Suppression techniques of subthreshold hump effect for. Mar 17, 2019 download subthreshold operation and gmid design cppsim book pdf free download link or read online here in pdf. In this paper, we present a 55nm deeply depleted channel ddc technology with ultralow leakage ull devices that is optimized for ulp subthreshold operation due to higher drive strength, reduced variation, and support for vdd scaling for the sram and logic. A subthreshold circuit has been shown to consume orders of magnitude less power than the regular. Pdf modeling subthreshold leakage current in general. Therefore, the subthreshold hump can define as a current summation of a parasitic edge transistor and main channel hv mosfet 7. Index termsleakage current, mismatch, subthreshold. As i know it has some exponential inside the eqn, but i could get it in any sources. An improved model for subthreshold leakage current in general transistor networks is proposed. Reducing subthreshold leakage power through hybrid mosfetnems power gating david g. Reducing subthreshold leakage power through hybrid mosfet. This thinking is starting to change as new frontiers in ultralow power begin to be exploited through precise control of subthreshold leakage currents. Subthreshold operation and gmid design cppsim pdf book.
It further discusses the advantage of subthreshold circuit in energy saving. Simultaneous subthreshold and gateoxide tunneling leakage. We also present detailed energyperformance models of the adaptive feedback equalizer circuit. Total leakage optimization strategies for multilevel caches. Accurate stacking effect macromodeling of leakage power in. Previous modeling, presented in the literature and originally focused on seriesparallel topologies. A highdensity subthreshold sram with dataindependent bitline leakage and virtual ground replica scheme taehyoung kim, jason liu, john keane, and chris h. Reducing the subthreshold and gatetunneling leakage of sram. Finfet subthreshold cmos for ultralowpower applications. To carry out the optimization methodology, medici template files are developed to simulate. The proposed leakage reduction technique proved to be more effective in reducing gate leakage current than subthreshold leakage current.
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